genesys2-ddr3-sdram-controller serptail · COMPLETED
DDR3 SDRAM controller port for Digilent Genesys 2, replacing the original custom PHY with Xilinx 7-Series MIG
github.com/serptail/genesys2-ddr3-sdram-controller · ★ 0 · Forks 0 · Size 72 KB
SUMMARY
Technologies 2
Scored 2
Observed 2
Practices 6
Evidence 2
Skips 0
COVERAGE
Analyzed 10 files · 5 commits · 0 API calls
TECHNOLOGIES & DEPTH
Markdown LANGUAGE Depth 70
1 files · PRODUCTION
Redis CACHE Depth 73
3 files · CONFIGURATION
PRACTICES
documentation · observedautomated_tests · absentcontinuous_integration · absentcontainerization · absentlinting · absentformatting · absent
ACTIVITY & OWNERSHIP
First commit 2026-08-21
Last commit 2026-08-22
Active months 1
Commits 5