chipgate kyal102 · COMPLETED
Deterministic structural sanity checker for Verilog RTL — undriven outputs, multi-driven signals, latch-inference risks, blocking/nonblocking misuse. Pure Python stdlib.
github.com/kyal102/chipgate · ★ 40 · Forks 2 · Size 4.4 MB
SUMMARY
Technologies 8
Scored 8
Observed 8
Practices 6
Evidence 10
Skips 0
COVERAGE
Analyzed 442 files · 17 commits · 0 API calls
TECHNOLOGIES & DEPTH
JSON LANGUAGE Depth 70
23 files · PRODUCTION
TOML LANGUAGE Depth 70
1 files · PRODUCTION
Markdown LANGUAGE Depth 70
40 files · PRODUCTION
YAML LANGUAGE Depth 70
4 files · PRODUCTION
Python LANGUAGE Depth 70
108 files · PRODUCTION
pip BUILD_TOOL Depth 80
1 files · CONFIGURATION
Poetry BUILD_TOOL Depth 80
1 files · CONFIGURATION
pytest TESTING Depth 53
6 files · TEST
PRACTICES
documentation · observedautomated_tests · observedcontinuous_integration · observedcontainerization · absentlinting · observedformatting · absent
ACTIVITY & OWNERSHIP
First commit 2026-06-26
Last commit 2026-07-08
Active months 2
Commits 17