RISC-16bit-Processor KHALEDNOAMAN · COMPLETED
16-Bit RISC Processor designed in Verilog with ALU, Control Unit, Register File, Data Memory, and Instruction Memory. Simulated using Icarus Verilog / ModelSim.
github.com/KHALEDNOAMAN/RISC-16bit-Processor · ★ 1 · Forks 0 · Size 39 KB
SUMMARY
Technologies 2
Scored 2
Observed 2
Practices 6
Evidence 2
Skips 0
COVERAGE
Analyzed 28 files · 35 commits · 0 API calls
TECHNOLOGIES & DEPTH
Markdown LANGUAGE Depth 70
9 files · PRODUCTION
YAML LANGUAGE Depth 70
1 files · PRODUCTION
PRACTICES
documentation · observedautomated_tests · observedcontinuous_integration · observedcontainerization · absentlinting · absentformatting · absent
ACTIVITY & OWNERSHIP
First commit 2026-08-05
Last commit 2026-09-13
Active months 2
Commits 35