Digital-Logic-Labs KHALEDNOAMAN · COMPLETED
Digital logic design lab assignments - combinational circuits, sequential circuits, FSMs, implemented in Verilog and simulated.
github.com/KHALEDNOAMAN/Digital-Logic-Labs · ★ 1 · Forks 0 · Size 37 KB
SUMMARY
Technologies 1
Scored 1
Observed 1
Practices 6
Evidence 1
Skips 0
COVERAGE
Analyzed 65 files · 73 commits · 0 API calls
TECHNOLOGIES & DEPTH
Markdown LANGUAGE Depth 70
13 files · PRODUCTION
PRACTICES
documentation · observedautomated_tests · observedcontinuous_integration · absentcontainerization · absentlinting · absentformatting · absent
ACTIVITY & OWNERSHIP
First commit 2026-08-05
Last commit 2026-09-13
Active months 2
Commits 73