Verilog_Test-Bench_Generator AshkanShakiba · COMPLETED
gets signals count and their names to print test bench that includes all situations
github.com/AshkanShakiba/Verilog_Test-Bench_Generator · ★ 1 · Forks 0 · Size 1 KB
SUMMARY
Technologies 2
Scored 2
Observed 2
Practices 6
Evidence 2
Skips 0
COVERAGE
Analyzed 2 files · 2 commits · 0 API calls
TECHNOLOGIES & DEPTH
Markdown LANGUAGE Depth 70
1 files · PRODUCTION
C LANGUAGE Depth 70
1 files · PRODUCTION
PRACTICES
documentation · observedautomated_tests · observedcontinuous_integration · absentcontainerization · absentlinting · absentformatting · absent
ACTIVITY & OWNERSHIP
First commit 2021-11-27
Last commit 2021-11-27
Active months 1
Commits 2