CXL-3.0-Zero-Copy-Enterprise-SAN-Mirror-Controller-IP Abhishek1033ubuntu · COMPLETED
Open-source, deterministic CXL 3.0 / PCIe 6.0 Enterprise SAN Mirror Controller IP core in SystemVerilog. Features sub-300ns write latency, <10ns hardware failover, and a 200ns inline SHA-256 deduplication engine for high-density flash arrays and memory pooling. Licensed under CERN-OHL-S-2.0.
github.com/Abhishek1033ubuntu/CXL-3.0-Zero-Copy-Enterprise-SAN-Mirror-Controller-IP · ★ 1 · Forks 0 · Size 42 KB
SUMMARY
Technologies 3
Scored 3
Observed 3
Practices 6
Evidence 3
Skips 0
COVERAGE
Analyzed 11 files · 17 commits · 0 API calls
TECHNOLOGIES & DEPTH
Markdown LANGUAGE Depth 70
3 files · PRODUCTION
Python LANGUAGE Depth 70
1 files · PRODUCTION
Redis CACHE Depth 65
1 files · CONFIGURATION
PRACTICES
documentation · observedautomated_tests · observedcontinuous_integration · absentcontainerization · absentlinting · absentformatting · absent
ACTIVITY & OWNERSHIP
First commit 2026-09-14
Last commit 2026-09-14
Active months 1
Commits 17